1. Field of the Invention
The present invention relates to a balanced transformer less (BTL) amplifying circuit which prevents saturation of a transistor to achieve a large output.
2. Description of the Related Art
Conventionally, BTL amplifying circuits are known as electric power amplifying circuits which generate, using input audio signals, signals having mutually inverted phases for use in BTL-driving a load. A typical BTL circuit has a structure as is shown in FIG. 3.
Referring to FIG. 3, the connection point a between driving transistors 4, 5 and the connection point b between output transistors 6, 7 are commonly connected, while the connection point c between driving transistors 8, 9 and the connection point d between output transistors 10, 11 are commonly connected.
With the above structure, when an input amplifier 1 receives a negative input signal, a negative signal is supplied to a first input transistor 2, while a positive signal is supplied to a second input transistor 3. In response to the supplied negative signal, the first input transistor 2 is turned off, upon which the driving transistor 4 is turned on and the driving transistor 5 is turned off. Further, the output transistor 6 is turned on and the output transistor 7 is turned off. In response to the supplied positive signal, the second input transistor 3 is turned on, upon which the driving transistor 8 is turned off and the driving transistor 9 is turned on. Further, the output transistor 10 is turned off and the output transistor 11 is turned on. As a result, an output current flows through the output transistor 6, a load 12, and the output transistor 11 in this order.
On the other hand, when an input amplifier 1 receives a positive input signal, a positive signal is supplied to the first input transistor 2, while a negative signal is supplied to the second input transistor 3. In response to the supplied positive signal, the first input transistor 2 is turned on, upon which the driving transistor 4 is turned off and the driving transistor 5 is turned on. Further, the output transistor 6 is turned off and the output transistor 7 is turned on. In response to the supplied negative signal, the second input transistor 3 is turned off, upon which the driving transistor 8 is turned on and the driving transistor 9 is turned off. Further, the output transistor 10 is turned on and the output transistor 11 is turned off. As a result, an output current flows through the output transistor 10, the load 12, and the output transistor 7 in this order.
As described above, the load 12 is BTL-driven by an output current flowing through either the output transistor 6, the load 12, and the output transistor 11 or the output transistor 10, the load 12, and the output transistor 7 in respective orders.
A saturation voltage on the power source voltage side of the BTL amplifying circuit shown in FIG. 3 is determined at the largest one of the Vce6(sat), Vce4(sat)+Vbe6, and Vbe4+Vce13(sat), wherein Vce6(sat), Vce4(sat), and Vce13(sat) are collector-emitter saturation voltages of the output transistor 6, the driving transistor 4, and the current source transistor 13, respectively, and Vbe6 and Vbe4 are base-emitter voltages of the output transistor 6 and the driving transistor 4, respectively. Here, since the output transistor 6 is set with large current supplying capacity in order to drive a load, the output transistor 6 resultantly has a large size. Since collector-emitter saturation voltage Vce(sat) of a transistor become smaller with an increasing size of the transistor, when the transistor 6 has a large size, Vce6(sat) and Vbe6 thereof becomes smaller then Vbe4+Vce13(sat) becomes the largest among the aforementioned three voltages. Therefore, the saturation voltage on the power source voltage side of the BLT amplifying circuit is determined at Vbe4+Vce13(sat). Based on a similar concept, the saturation voltage on the power source voltage side of the third and fourth output transistors 10 and 11 are determined according to the base-emitter voltage Vbe8 of the driving transistor 8 and the collector-emitter saturation voltage Vce14(sat) of the current source transistor 14, respectively.
When the saturation voltage of a BTL amplifying circuit is determined as above, the upper limit of the swing of an output signal is determined at a value lower than the power source voltage Vcc by Vbe4+Vce13(sat), while the lower limit thereof is determined at a value higher than the earth level by Vbe8+Vce14(sat). As Vbe+Vce(sat) is not negligible compared to the power source voltage Vcc, the full-swing level of an output signal from the BTL amplifying circuit is remarkably limited. This hinders an increase of an output of a BTL amplifying circuit to achieve a BTL amplifying circuit with a large output.